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Toshiba Develop Newer SRAM for Lower Power Consumption in Mobile Devices



/ 4 years ago

Japanese-based Industry giant Toshiba recently announced that they’re developing a technology with a promise that it will be making a substantial cut in power consumption for embedded SRAM solutions which is used in smartphones, tablets, MP3 players and such portable devices which use high-performance memory modules. The company believes that this technology may be used to save significant amounts of battery power.

However, what Toshiba claim is that the embedded memory chips could have power usage lowered by as low as 27% on a device with power saving features enabled, but when used. On standby, Toshiba assures that it should be able to save up to a surprising 85% of memory chip power consumption.

Toshiba was able to do this by implementing a  few circuits and not re-designing the SRAM or introducing a new memory type. The changes will have temperature sensitivity, predictive capability and will even be able to dynamically adjust its performance depending on the load.

Toshiba said the following in its press release:

Toshiba’s new technology applies a BLPC and DCRC. The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits. The DCRC greatly decreases standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver.

Toshiba wasn’t exactly clear about the actual savings of power consumption in smartphones and such portable devices. It is presumed that due to the the role of the memory chip, it still consumes power after locking the device or turning the screen off. Additionally higher memory chip counts lead to even more power consumption and therefore it is something that needs to be addressed. Toshiba’s solution may be one of the ways to address that issue especially at a time when on-board memory of such devices are beginning to grow to 2GB and even beyond.

Maybe smaller die-shrinks and other technology implementations could help to reduce power consumption even more in the future.


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