AMD Elaborates on Vega Architecture and High Bandwidth Cache Controller
Samuel Wan / 3 months ago
During the Capsaicin and Cream event yesterday, AMD once again showed off key elements of their upcoming Vega architecture. Set to replace the current GCN based designs, the new architecture aims to offer a full leap ahead in terms of performance and features. While the event was somewhat developer focused, AMD has elaborated on some key features they’ve only previously mentioned in passing.
One of the most important changes is the new High Bandwidth Cache Controller. As you know, GPUs nearly always feature a VRAM cache to store their working data. However, the amount of memory available and the all important bandwidth are both limited. This is where the HBCC comes in. As a smart controller, it better optimizes the VRAM to store only required materials and tosses out the useless ones. It also optimizes the transfers to make the use of the limited bandwidth. This builds on top of early technology we saw with Fiji where AMD was able to stretch out the 4GB of HBM2 to match even 6GB or more Nvidia GPUs. AMD is claiming 50% improved AVG FPS and a doubling of the MIN FPS.
Another addition to Vega is Rapid Packed Math. This allows Vega to switch on the fly from FP32 workload to FP16 workload. For features like hair, TressFX will now allow the use of FP16, effectively doubling performance relative to regular FP32. This allows for doubling of on-screen objects, in this case hair. Since hair modeling doesn’t need to be 100% accurate in most cases, this should either reduce the impact of TressFX or allow for more hair.
Last of all, we have the improved virtualization abilities of Vega. This Radeon Virtualized Encoding allows companies to more optimally virtualize Radeon GPUs to get the most out of time. While game streaming is the obvious application, there will likely be other uses for this technology as well. Finally, AMD went over their new Next Compute Unit and other Vega updates without any new details.