In its recent Financial Analyst Day, AMD presented an updated roadmap that highlights the server processors EPYC Venice, based on Zen 6, promising a generational leap in performance for data centers.
According to internal projections, the EPYC Venice CPUs with Zen 6 will offer a combined improvement of more than 70% in performance and efficiency compared with the previous generation (Zen 5 “EPYC Turin”). This figure was measured using the industry-standard SPECrate 2017 INT test on a dual-socket (2P) platform, confirming that the improvements apply to overall compute performance and are not limited solely to artificial intelligence.
A Major Jump in Performance and Efficiency
On top of this increase, the EPYC Venice line will also feature more than a 30% improvement in thread count: we could see processors reaching up to 256 cores and 512 threads in the highest tier, a 33.3% increase over the maximum of 192 cores in Turin.
Much of this advancement is due to the transition to TSMC’s 2 nm manufacturing node. This new process node marks a crucial shift from FinFET transistors to Nanosheet (GAA). The 2 nm node offers major optimization, delivering up to 15% more performance at the same power consumption, or a reduction in power consumption of up to 30% while maintaining the same performance.
The 70% leap comes from a combination of the 2 nm process, the increased core count, and the architectural improvements in the Zen 6 cores themselves—such as improvements in IPC (instructions per clock).
Although the initial details focus on servers, AMD has confirmed that the 2 nm technology will also extend to client processors, including the Ryzen desktop series “Olympic Ridge” and laptop series “Medusa/Gator”.
With Zen 6, AMD is not only seeking to consolidate its leadership in data-centers with its EPYC processors—and everything indicates it will succeed.
