AMD is preparing to take another major step forward with its Zen 6 architecture, and early details about the new Core Complex Die (CCD) are already very promising. According to information shared by well-known leaker HXL (@9550pro), Zen 6 will use TSMC’s N2 (2 nm) process, based on NanoSheet technology.
The CCD is expected to measure around 76 mm2, only slightly larger than Zen 4 and Zen 5, but with a much bigger increase in internal resources. AMD is aiming to deliver 12 cores and 48 MB of L3 cache per CCD, which represents a 50% increase in both cores and cache compared to previous generations.
Zen 6 Compared to Previous Generations
Looking at past designs makes the progress even clearer. Zen 4 and Zen 5, built on TSMC’s N5 and N4 nodes, offered 8 cores and 32 MB of L3 cache in an area of about 71–72 mm2. With Zen 6, AMD manages to add four more cores and significantly more cache while keeping the die size almost the same.
The increase in surface area is limited to roughly 5–7%, highlighting the impressive density of TSMC’s N2 process. AMD has already confirmed that EPYC Venice server CPUs will be the first commercial products based on Zen 6 and the N2 node. Rumors also suggest that the full Zen 6 lineup will use an N2P variant for the CCDs, while the I/O die will remain on N3P.
Expectations for Zen 6 are especially high on the desktop side. Future Ryzen Zen 6 CPUs are rumored to offer double-digit IPC gains, higher clock speeds, faster DDR5 memory support, and configurations of up to 24 cores and 48 threads using two CCDs.
There is also talk of further improvements to 3D V-Cache, which is expected to reach its third generation. This should bring additional performance gains in gaming and workloads that are sensitive to cache latency.
