ASUS Extreme Engine DIGI+ IV – Getting Technical
The number of phases in a VRM is not the determining factor of the VRM quality and therefore its performance. This is something a lot of people are not aware of, indeed most people aren’t even aware of what CPU VRM phases are either so knowing that “more is better” is considered fairly advanced knowledge in itself. Yet more is not better, the quality of the components used and the way they are implemented are crucial to what is better. The new ASUS Extreme Engine DIGI+ IV deploys this philosophy. The two highlights are the use of a new PowIRstage combo driver and MicroFine Alloy Chokes.
The PowerIRstage combo unifies the MOSFET driver, high side MOSFETs and low side MOSFETs into one chip. This implifies the VRM chain making it more electrically efficient.
The combination of the PowIRstage combo and a new RDS (resistance drain to source) on sense allows for much tighter tolerancies in the ASUS VRM compared to “traditional” VRM designs.
The next flagship VRM feature is the use of MicroFine Alloy chokes. ASUS claim these reduce hysteresis loss, eddy current loss, inductance loss, increase permeability and lower the overall operating temperature. Those things are all achieved simply by having smaller alloy particles within the solid alloy chokes: remember that alloy chokes on their own are already a large upgrade on traditional coil based chokes.
The last part of the advanced VRM design is a new pulse width modulator for the memory VRM, this boosts the frequency of the memory VRM from 500 kHz to 1000 kHz which ASUS claim reduces DC ripple by up to 40%.
