Intel Debuts First 10nm Cannon Lake Processor



/ 1 week ago

Intel

Intel’s First Cannon Lake CPU Core i3 8121U

A few years ago, Intel started extending each new process node. Due to the complexities of silicon development, moving to a new process every two years was unsustainable. Starting with 22nm, the delays started to pile on. Eventually, Intel formalized the delays under their new product strategy. Due to numerous issues, 10nm chips have been a long time coming. This week, Intel has finally launched their first 10nm chip.

The first 10nm processor from Intel is part of the Cannon Lake family. The original plans called for a  10nm debut in 2015. As we all know, 14nm took a lot longer than expected to arrive. 10nm has been even worse in terms of delays. Even now, mass production has been viable. However, Intel is shipping a single 10nm processor. The customer is the Lenovo and the new Core i3 8121U chip is meant for the Chinese market.

Lenovo Pairs Cannon Lake With AMD GPU

The new Core i3 8121U as expected is a mobile lower power CPU. Just like before, the new process is debuting on mobile first. The new chip comes at a base frequency of 2.2 GHz with a boost to 3.2 GHz. This is in line with the latest Kaby Lake and Coffee Lake chips. Interestingly there is no iGPU listed and Lenovo paired the CPU with the AMD Radeon RX 540 2GB. Perhaps the exclusion of an iGPU helps boost yields due to the smaller die size.

There are also upgrade in other areas for the chip. LPDDR4 and LPDDR4X running at 2400 both get support. This gives a max memory bandwidth of 41.6 GH/s, a boost of about 15%. This should be a nice boost for future Intel iGPUs. Finally, the chip has 4MB of L3 cache with a 15W TDP. It is unclear when the rest of the lineup will arrive but hopefully, late 2018 or early 2019 will see the rest of the lineup.

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Comments

One Response to “Intel Debuts First 10nm Cannon Lake Processor”
  1. Sykobee says:

    Skylake U (2+2) was 102mm^2 on 14nm.
    The scaling for 10nm Intel is 0.63x for an SRAM cell (i.e., a 10nm SRAM cell is 0.63x 14nm SRAM cell size).
    Using simple scaling, CNL-U (2+2) would be between 60 and 70mm^2 (depending on I/O scaling and uncore changes such as LPDDR4 support).
    This is a tiny die, and the fact that the graphics is disabled out of necessity shows just how terrible Intel’s 10nm process is, if they cannot even get such small dies right.

    Additionally, this die will have under 2B transistors, given SKL-U had around 1.8B. Apple’s A11 has over 4B transistors on an 88mm^2 10nm TSMC die. Tell me again about Intel’s transistor density advantage…

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