After years of strategic restructuring, Intel‘s bets on advanced manufacturing are starting to pay off. The company has just reached a key milestone by producing its one-millionth test wafer using high numerical aperture lithography (High-NA EUV), putting it between two and four years ahead of its main rivals in the semiconductor industry.
While Samsung plans to integrate ASML’s complex High-NA machines by 2028 and TSMC plans to do so by 2030, Intel has already built up an important amount of operational testing with this technology. High-NA EUV cuts the exposure field in half, allowing much more precise patterns to be printed in a single pass. This removes the need for costly multi-patterning at geometries below 3 nanometers, an important step for successfully scaling nodes such as Intel 14A, which the company is working on right now.
Intel Hits 1 Million High-NA EUV Wafers, Putting It Years Ahead of TSMC and Samsung
This progress in lithography comes together with excellent news for the Intel Foundry division in the area of 3D packaging. A recent UBS analysis shows a high level of confidence from the industry in EMIB-T technology (Embedded Multi-die Interconnect Bridge with through-silicon vias), highlighting its high production yields and execution accuracy. Because of this, very important customers could be choosing it as an alternative to TSMC, which is currently the largest manufacturer of advanced semiconductors in the industry.
UBS estimates that Intel will have enough capacity to deliver more than 2 million EMIB-T substrates by 2028, mainly to meet demand for Google’s TPU v9 processors, developed together with MediaTek, including chips on the 2nm node.
A key factor will be cost, as Intel’s EMIB-T solution is around 50% cheaper than TSMC’s CoWoS technology, so large companies have a clear choice about where they should place their bets.
