TSMC Announces 6-Nanometer Process Technology

Featuring Higher Transistor Density

Taiwan Semiconductor Manufacturing Company (TSMC) has announced their new 6nm manufacturing technology. This follows after the announcement of their 5nm entering risk production last week.

Despite the small number change, this fabrication process features a considerably higher transistor density in comparison to 7nm.

It is in fact an evolution of this process, utilizing the same design rules but TSMC claims it has 18% higher logic density. Existing designs developed using N7 can now be shrunk by 15% to N6.

According to the company, this new N6 leverages new capabilities in extreme ultraviolet lithograpy (EUVL). Although so far, they have not revealed how exactly. It is possible that they are reserving more information until the TSMC Technology Symposium next week in Santa Clara, California.

When Will TSMC’s 6nm Process Arrive?

TSMC expects 6nm to enter risk production in the first quarter of next year. As for 6nm products, expect these to arrive around 2021.

Ron Perillo

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