ARM 28nm Cortex A9 reaches 3.1GHz

/ 4 years ago

TSMC today announced its 28 nm high performance ARM Cortex-A9 dual-core processor test chip achieved 3.1 GHz performance under typical conditions.

The TSMC 28 nm HPM (high performance for mobile applications) process technology that achieved these results addresses applications requiring both high speed and low leakage power. Using various design signoff conditions, ARM A9 at TSMC 28HPM delivers performance speed range from 1.5 GHz to 2.0 GHz, suitable for mobile computing, and up to 3.1 GHz for high-performance uses. With its wide performance-to-leakage coverage, the 28 nm HPM process was developed for devices targeting networking, tablet and mobile consumer product applications.
The ARM Cortex-A9 silicon implementation and validation is part of TSMC’s ongoing technology benchmarking effort to demonstrate performance, power and area (PPA) capabilities at the system-on-chip (SoC) level for each process technology node.

“At 3.1 GHz this 28HPM dual-core processor implementation is twice as fast as its counterpart at TSMC 40 nm under the same operating conditions,” said Cliff Hou, TSMC Vice President, Research & Development. “This work demonstrates how ARM and TSMC can satisfy high performance market demands. With other implementation options, 28HPM is also highly suited for a wide range of markets that prize performance and power efficiency.”

“TSMC’s high performance 28HPM process is suitable for a wide range of advanced ARM-processor based applications, extending from high-frequency, performance-orientated computing devices to power sensitive applications,” said Jim Nicholas, Vice President of Marketing, Processor Division, ARM. “The collaboration between ARM, TSMC and our ecosystem partners has delivered an extensible implementation platform that enables flexibility in performance and power management tradeoffs for next generation products.”

The Cortex-A9 processor is available for license from ARM and is aimed at mobile, high-performance consumer, and enterprise SoC requiring high performance and low power.

The test chip results demonstrate that the combination of the most advanced process technology, best-practices circuit design techniques, and proven chip implementation methodology lead to the highest PPA landmark in an SoC. The results confirm the benefits of TSMC’s Open Innovation Platform (OIP) design ecosystem that promotes innovation for the semiconductor design community, ecosystem partners and TSMC’s complete technology portfolio.

Source: PR