New Hybrid Memory Cube Designed To Boost DRAM Bandwidth By 15x
Roshan Ashraf Shaikh / 4 years ago
Micron, Samsung and Hynix, 3 of the largest Flash NAND manufacturers, with a support from a 100 tech companies, have announced that the final specifications of a 3 dimensional DRAM called ‘Hybrid Memory Cube’. According to the claim made by the Hybrid memory cube consortium, it will increase performance for networking and for high performance computing requirements.
This technology uses stacks of multiple DRAM memory chips over the DRAM controller. This possible using Vertical Interconnect Access technology which is a method that passes an electric wire through the DRAM chips vertically. It also decided the load on DRAM since the chips are stacked on top of eachother over the controller, therefore the distance between them is significantly shorter without any need of circuit board traces.
There are 2 physical interfaces between the system’s processor and the memory cube: short reach and ultra-short teach. Short Reach is practically similar to what traditional memory stick maintains with the CPU with a distance of no more than 10 inches. The application of this method will help network application can provide a throughput of 15-28 Gbps per pin.
Ultra-short method is primarily for low energy consumption and a much lesser proximity design for high performance networking, testing and measuring requirements with a distance of 3 inch between the memory block and the CPU. This will provide a throughput of 15Gbps.
The initial Memory Cube will be with 2GB and 4GB variants and provides bi-directional bandwidth of upto 160GBps, more than what DDR3 and DDR4 spec allows.
Mike Black, the chief technology Strategist said,”We took the logic portion of the DRAM functionality out of it and dropped that into the logic chip that sits at the base of that 3D stack. That logic process allows us to take advantage of higher performance transistors … to not only interact up through the DRAM on top of it, but in a high-performance, efficient manner across a channel to a host processor. So that logic layer serves both as the host interface connection as well as the memory controller for the DRAM sitting on top of it”
Source: Computer World