AMD May Not Be Using Chiplets For Ryzen 3000
Samuel Wan / 2 years ago
AMD May Be Reserving Chiplets for EPYC and HEDT
Late last year, AMD unveiled their new designs for 2019 and forwards. Chief among them was the new Rome platform for the enterprise. The company debuted the new design with 2 new features. First was the new Zen 2 architecture with a massive IPC boost over Zen+. The second was the innovate new chiplet approach to designing CPUs. While the assumption was that Ryzen 3000, the new mainstream lineup would use chiplets, that may not be the case.
As a quick refresher, the new chiplet approach is the AMD strategy to handle core count scaling. By separating the I/O portion of the die and the CPU side, AMD is better able to scale designs beyond the basic 8 core MCM. It also allows the I/O portion which is less sensitive to clock speeds and power to use older 14nm process, while the CPU chiplets use 7nm to get peak performance. While AMD clearly aimed chiplets at EPYC enterprise chips, the consumer side would benefit too.
Chiplets Won’t Make Sense if Ryzen 3000 Limited to 8 Cores
According to the news from several sources, it appears that chiplets may remain an enterprise or HEDT feature for now. The basic AMD die still remains the 8 core MCM with the 4 core CCX. This means for a Ryzen 3000 chip with 8 cores, the chiplet approach might not make much sense. Breaking out the chiplet and I/O may not be worth it due to latency and cost concerns. The chiplet design only really starts paying off in full after at least 16 cores, and preferably more.
As it stands, if this report holds true, it might mean that Ryzen 3000 will be limited to 8 cores. For the mainstream, this still remains plenty. AMD has already pushed the default core count for the mainstream lineup from 4 to 8 with Ryzen. Perhaps the company will wait a bit longer before moving the market onto 12 or 16 cores. However, the HEDT Threadripper lineup should use the chiplet approach given their higher core counts. Either way, we should find out soon at CES.