AMD Unveils Zen 2 EPYC 7nm CPU with 25% Performance Gain
Ron Perillo / 6 months ago
AMD Introduces “Rome”
Following up Intel’s announcement of new Xeon server processors recently, AMD is firing a return salvo of their own to lay claim to more real estate in the enterprise CPU market. This time, their announcement does not include a rehash or glued-together previously released parts like Intel’s. But rather, they have unveiled their next generation EPYC CPU dubbed “Rome”.
AMD can now claim that they have the world’s first 7nm datacenter CPU. This not only brings increased IPC and significant total performance uplift, it also brings enhanced security features. Now pushing up to 64 cores/128 threads, up from the 32 cores/64 threads of the previous gen “Naples” EPYC CPUs.
The roadmap for Zen started with the first design in 2012. The first one being a 14nm processor, while the Zen+ update brought it down to 12nm. The next jump with Zen 2 is much larger at 7nm. Meanwhile, competitor Intel is struggling to meet production demands with their existing 14nm product line, since they are having production problems with 10nm. Futhermore, this has also waylaid Intel’s plans for significant performance improvements. So the company has been stuck adding ++++ optimizations to their 14nm line which has remained relatively the same for a while now.
What about Security Features?
The topic of security is also an unavoidable issue that needs to be discussed. Especially in light of Intel’s issues with Spectre and Meltdown. These ROME CPUs however have hardware mitigations for Spectre. Furthermore, AMD has increased the number of encryption keys for virtualizations for increased virtual machine support.
What is New with 7nm Zen Processors?
Moving down a full node to 7nm allows AMD to do more things with the Zen architecture. For instance, they can double chip density by two while halving the power consumption. According to AMD, the performance uplift is 25% over their current 12nm Zen+ offering.
With these “ROME” EPYC CPUs, the new architecture design also features improved branch prediction, instruction prefetch and re-optimized micro-op instruction cache, which has also been increased in size. Furthermore, ROME processors have double floating point width to 256-bit, and has double load store bandwidth with increased dispatch and retire bandwidth.
AMD is looking to stay with 7nm for a while, up at least until Zen 3 in 2020. Although, obviously, and hopefully, not as long as Intel with their 14nm++++.